Last Updated on July 3, 2023 by Mayank Dham
A full adder circuit is a crucial component in digital logic systems, designed to add three binary digits together: two input bits (A and B) and a carry-in bit (Cin). It serves as an extension to the half adder circuit, enabling the addition of multiple bits with the inclusion of the carry-in. The full adder circuit produces two outputs: a sum bit (S) and a carry-out bit (Cout). The sum bit represents the result of the addition of the three input bits, while the carry-out bit indicates the carry generated from the addition. By cascading multiple full adders, complex arithmetic operations on binary numbers can be performed accurately. Understanding the functionality and implementation of the full adder circuit is essential in various fields, including computer architecture, digital systems design, and arithmetic circuits.
How does Full Adder Work?
Full Adder is a combinational logic circuit that performs two Ex-OR, two AND and one OR operations. It is used in Processors and Multiple Bit addition and also goes by the name of Ripple-Carry Adder Below is an illustration that can help one understand how the Full Adder functions on input to produce output. Full Adder works in a manner that it can compute through a byte-wide adder and cascade the carry bit to another adder.
From the above image, we can understand the three input directing towards the left side of the full adder and directing outwards from from the full adder on right hand side as output.
Full Adder Truth Table
Now that we are done figuring out the principles on how the full adder circuit works, let us look at the full adder truth table on what we obtain as output for each scenario of input.
Given in the full adder truth table, we can verify the eight different rows as combination among these variables with A, B and C-IN as the input values and SUM and C-OUT as the obtained output values. To get to know the working, logic of the computation is as follow:-
Logic to Find SUM:-
The equation to compute can be, A’ B’ C-IN + A’ B C-IN’ + A B’ C-IN’ + A B C-IN —- Equation 1.
On further compressing Equation we obtain,
C-IN (A’ B’ + A B) + C-IN’ (A’ B + A B’)
Thus, we can obtain the final result that can be easy to implement as:-
C-IN XOR (A XOR B)
Logic to Find C-OUT:-
The equation to compute can be, A’ B C-IN + A B’ C-IN + A B C-IN’ + A B C-IN—- Equation 1.
On further compressing Equation we obtain,
A B + B C-IN + A C-IN
Another method through which C-OUT can be implemented:
A B + A C-IN + B C-IN (A + A’)
= A B C-IN + A B + A C-IN + A’ B C-IN
= A B (1 +C-IN) + A C-IN + A’ B C-IN
= A B + A C-IN + A’ B C-IN
= A B + A C-IN (B + B’) + A’ B C-IN
= A B C-IN + A B + A B’ C-IN + A’ B C-IN
= A B (C-IN + 1) + A B’ C-IN + A’ B C-IN
= A B + A B’ C-IN + A’ B C-IN
= AB + C-IN (A’ B + A B’)
COUT = AB + C-IN (A EX – OR B)
Implementation of Full Adder
Now that we have a strong idea of full adder truth table, let us proceed to see how combinational full adder circuit can be made in a step-by-step manner.
1. Using Two Half Adder
Full Adder can be implemented using two half adders to obtain the output by placing them together. The full adder circuit can be designed as follow.
The following illustration shows clearly the generation of output at each part of the full adder circuit composed through two half adders making the logic easy to understand.
2. Using NAND Gate
Full Adder can also be implemented using NAND where in total, nine NAND gates will be required to get the desired outputs. The illustration can be given as follow:-
3. Using NOR Gate
NOR Gate is another gate that can be universally applicable on logic design and same is the case with Full Adder. The Full Adder Circuit implementation can be as follow:-
As we approach towards the commencement of the article, we explored in this article about Full Adder and understood in detail about Full Adder Truth Table and Full Adder Circuit. Now that we have firm grip on the topic, it will be helpful in providing strong logic design knowledge. We hope you liked this article on Full Adder and hope to see you again at PrepBytes with another informative piece of article from our side.
FAQs Related to Full Adder
1. State the differences between Half Adder and Full Adder.
The differences between the both are as follow.
|Full Adder||Half Adder|
|1.It has three inputs||1. It has only two inputs|
|2. It can not be used as Half Adder Circuit.||2. It cannot be used as Full Adder Circuit.|
|3. Used to add multiple bits.||3. Used in calculators and digital devices|
|4. It comprises of two XOR, two AND and one OR gate.||4. It comprises of one XOR and one AND gate.|
Q2. Is the previous carry used in Full Adder?
Yes, the previous carry is used in a Full Adder. A Full Adder is a digital logic circuit used to add three binary inputs: A, B, and a carry-in (C-in). The carry-in represents the carry bit from the previous stage of addition. The Full Adder generates two outputs: the sum (S) and the carry-out (C-out). The carry-out bit is produced based on the input bits and the carry-in, which allows for the addition of multiple bits together in cascaded adders.
Q3. Is there an alternative name for Full Adder, if so, then what?
An alternative name for Full Adder is "Three-input Adder." This name refers to the fact that a Full Adder takes three inputs: two binary digits to be added (A and B) and a carry-in (C-in). It distinguishes it from a Half Adder, which only takes two inputs.
Q4. Discuss about the input in Full Adder?
The input in a Full Adder consists of three binary signals: A, B, and C-in.
- A and B represent the two binary digits to be added together.
C-in (carry-in) represents the carry bit from the previous stage of addition. It is the carry generated when adding the previous bits.
The Full Adder circuit combines these inputs to produce two outputs: the sum (S) and the carry-out (C-out). The sum output represents the binary sum of A, B, and C-in, while the carry-out represents the carry generated by the addition.The input bits in a Full Adder determine the resulting sum and carry-out, allowing for the addition of multiple bits in cascaded adder circuits.