Last Updated on June 12, 2023 by Mayank Dham
Previously, the basic operation of computers was to represent and store numbers. However, when computers came with computation, such as manipulating numbers such as adding and multiplying, these operations were handled by the computer’s ALU or arithmetic logic unit.
The central processing unit (CPU) is split into two parts:
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Memory, registers, adders, ALU, and communication buses are all part of the data section. Each step (fetching, decoding, executing, and saving the result) necessitates communication (data transfer) paths between memory, registers, and ALU. It is also referred to as the data path.
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Control section: Control signals configure data flow directions on communication buses and select ALU and memory functions to establish each step’s data path. A control unit composed of one or more finite state machines generates control signals.
Dath Path
Assume that any data processing operation, such as transferring the content of a register from one location to another, from one register to another register, performing the addition of two numbers in ALU, copying something in memory, and copying to register, should be performed in the CPU. So, any data processing operation occurs in the CPU, and data for that data operation follows a specific path known as the "data path."
A data path is a collection of functional units that perform data processing operations, such as arithmetic logic units or multipliers, registers, and buses. It is made up of the central processing unit (CPU) and the control unit. A larger data path can be made by joining more than one data path using multiplexers. A data path is the set of registers and the internal buses of the CPU that allow data to flow between them. The most basic CPU design employs a single common internal bus, while efficient addition necessitates a slightly more complicated three-internal-bus structure. Many simple CPUs have a two-read, one-write register file connected to the ALU’s two inputs and one output.
1. Arithmetic Logic Unit (ALU)
The ALU is a computer’s mathematical brain. The arithmetic and logic unit (ALU) is a digital circuit that performs arithmetic and logic operations. It is the fundamental building block of a computer’s central processing unit. It is present in every CPU and is used to perform operations such as addition, subtraction, division, and multiplication, among others. It is the main component of the system that uses logic to carry out a specific instruction or program. ALU accepts two operands as input and function code, and it can perform a variety of functions such as subtraction, X-NOR, division, and many others.
Aside from the ALU, modern CPUs include a control unit and a set of registers. The majority of operations are carried out by one or more ALUs, which load data from the input register. Registers are a small amount of storage available to the CPU that can be accessed quickly. The control unit instructs the ALU on the operation to be performed on the available data. The ALU stores the output of a calculation or manipulation in an output register.
2. Registers
Registers act as gates in this context, sending signals to components to perform micro-operations. The control unit directs register signals and controls the registers. Here are five registers used to store in-out signal data:
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Program Counter
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The program counter (PC) in the computer processor is a CPU register that contains the address of the next instruction to be executed from memory. As each instruction is retrieved, the program counter adds one to its stored value. It is a digital counter that is required for faster task execution and tracking the current execution point.
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Instruction Register
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An instruction register (IR) is a component of a CPU’s control unit that stores the instruction that is currently being executed or decoded. An instruction register is a component of a CPU’s control unit that stores the current instruction being executed or decoded. The instruction register specifically holds the instruction and provides it to the instruction decoder circuit.
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Memory Address Register
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The Memory Address Register (MAR) is a CPU register that stores either the memory address from which data is retrieved from the CPU or the address to which data is sent and stored. It is a CPU (central processing unit) temporary storage component that temporarily stores the address (location) of the data sent by the memory unit until the instruction for the specific data is executed.
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Memory Data Register
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The memory data register (MDR) is a register in a computer’s processor, or central processing unit, CPU, that stores data transferred to and from immediate access storage. Memory data register (MDR) and memory buffer register (MBR) are synonyms.
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General Purpose Register
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General-purpose registers are multipurpose registers that are used to store temporary data within the microprocessor. They can be used by both programmers and users.
3. BUS
The bus in early computers consisted of parallel electrical wires with multiple hardware connections. As a result, a bus is a communication system that transfers data between computer components or between computers. It consists of both hardware components such as wires and optical fibers, as well as software such as communication protocols. The Registers, ALU, and the interconnecting BUS are referred to collectively as data paths. Here are the following types of buses:
1. Address bus: A bus that transports addresses.
2. Data buses: These are buses that transport data.
3. Control bus: If the bus transports control signals.
4. Power bus: A power bus is one that transports clock pulses and power signals.
The bus can be used for either a single or multiple purposes. When we have different types of buses, we will have different types of bus organizations, such as:
One Bus organization
A single bus is used for multiple purposes in one bus organization. The single bus connects a collection of general-purpose registers, program counters, instruction registers, memory address registers (MAR), and memory data registers (MDR). Memory read/write can be accomplished using MAR and MDR.
The program counterpoints to the memory location where the next instruction will be retrieved. The current instruction will be copied into the instruction register. Only one operand can be read from the bus at a time in one bus organization. If the operation requires reading two operands, the read operation must be performed twice. As a result, the process is taking a little longer. One of the benefits of one bus organization is that it is one of the simplest and cheapest to implement. At the same time, it has the disadvantage of only having one bus. All general-purpose registers, program counters, instruction registers, MARs, and MDRs access this "one bus," making every operation sequential. This architecture is no longer recommended.
Two Bus organizations
This overcame the disadvantage of one bus organization, and another architecture known as two bus organization was developed. There are two buses in two bus organizations, and the general-purpose register can read/write from both buses. Because of the two buses, two operands can be fetched at the same time in this case.
One bus fetch operand for the ALU and another for the register. When both buses are busy fetching operands, the output can be saved in a temporary register. When the buses are free, the specific output can be dropped on them.
There are two types of bus organizations: in-bus and out-bus. The general-purpose register has the ability to read data from the in-bus and write data to the out-bus. Here buses get dedicated.
Three Bus organization
We have three buses in three bus organizations: OUT bus 1, OUT bus 2, and an IN bus. We can get the operand from the out buses, which can come from the general-purpose register and be evaluated in ALU, and the output is dropped on the In Bus to be sent to the respective registers.
This implementation is more complicated, but it is faster because two operands can flow into and out of the ALU in parallel. It was developed to overcome the "busy waiting" problem of two bus organizations.
Conclusion
The ALU and data path are essential components of a computer’s CPU. The ALU performs arithmetic and logical operations, while the data path facilitates data movement and manipulation. Their integration enables the CPU to execute instructions and process data efficiently. Together, they form the backbone of a computer’s processing capabilities.
Frequently Asked Questions (FAQs)
Q1. What is the purpose of the ALU in a CPU?
The Arithmetic Logic Unit (ALU) is responsible for performing arithmetic operations (addition, subtraction, multiplication, and division) and logical operations (AND, OR, NOT) within a CPU. It carries out these operations on input data and produces the desired output results.
Q2.How does the data path facilitate data movement within the CPU?
The data path consists of registers, multiplexers, decoders, and buses that enable the flow of data within the CPU. Registers store temporary data, multiplexers select inputs, decoders route data to the appropriate components, and buses transfer data between registers, memory, and the ALU.
Q3. What is the relationship between the ALU and the data path?
The ALU and data path work together in the CPU. The data path provides the infrastructure for data movement and manipulation, allowing instructions and data to flow between registers, memory, and the ALU. The ALU, in turn, performs calculations and logical operations on the data received from the data path.
Q4. How do the ALU and data path contribute to CPU performance?
The ALU and data path play a crucial role in CPU performance. The ALU’s ability to perform calculations and logical operations quickly enables efficient execution of instructions. The data path ensures smooth data flow, minimizing delays and facilitating faster processing of data within the CPU.
Q5. Can the ALU and data path be customized or expanded on a CPU?
Yes, the ALU and data path can be customized or expanded depending on the specific requirements of a CPU. Different architectures may have variations in the design and capabilities of the ALU and data path, allowing for optimization and specialization based on the intended use of the CPU.